6DD3460-0AC0

6DD3460-0AC0

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6DD3460-0AC0

　如图1所示，典型的16位并行闪存每秒传输速率为20Mb。对于使用32位微控制器和32位外部闪存通信总线的系统(如恩智浦产品)，设计人员可以选择使用两个16位并行闪存达到40Mb/s的传输速率。但是，增加速度的同时也会增加成本。这种配置使用两个独立的并行闪存，每个闪存有数十个封装管脚，无论是封装尺寸、管脚数量，还是PCB空间占用，都会远远超出设计人员的承受范围。

　　串行闪存通常使用简单的四针串行外设接口(SPI),从空间占用、功耗和成本等因素考虑是并行闪存的理想替代产品，但是传输速率非常低。通过图1我们可以看到典型SPI闪存50MHz的传输速率仅为5Mb/s，而采用两个16位并行闪存配置系统的传输速率是其8倍。另一个问题就是大多数微控制器SPI接口都与MCU外设矩阵连接，处理器访问数据前必须先由驱动器代码接收到内容并保存在板载RAM中。由于每次读取串行闪存都要通过SPI软件层，因此速度无法提高。对于采用标准SPI接口的外部闪存应用，速度可能无法满足要求。

　　新型四通道SPI闪存采用改进的6针SPI配置，数据传输速率远高于传统的SPI接口。如图1所示，四通道SPI每秒zui大传输速率可达40Mb，与两个16位并行闪存速度相当。由于减少了管脚数量和封装尺寸，与并行方案相比，四通道SPI串行闪存可有效降低成本。虽然四通道SPI闪存*可替代嵌入式系统中的并行闪存，但目前32位微控制器设计并不支持四通道SPI闪存的zui大传输速率。这主要是因为四通道SPI接口与传统的SPI接口连接方式相同，直接连接了微控制器外设矩阵。

　　解决外部闪存选型难题

　　恩智浦新开发的SPI闪存接口(SPIFI)可以*解决并行/串行闪存的选型困扰。已申请的SPIFI外设可以将低成本SPI和新型四通道SPI闪存映像到ARM Cortex-M3内存中。与外部并行闪存方案相比，使用SPI外部闪存的MCU性能损失非常小。由于外部SPI闪存完整的内存空间可以映像到MCU内存中，微控制器对外部闪存直接访问，无需使用软件API或库。

　　例如，使用四通道SPI闪存，SPIFI外设传输速率可达40Mb/s。设计人员可以选择更便宜的SPI闪存器件，在保证性能的基础上缩小脚位尺寸，简化配置。由于系统无需针对外部并行闪存使用庞大的接口设计，设计人员还可以选择体积更小、成本更低的微控制器。嵌入式系统采用SPIFI外设可以提高内存资源利用率，缩小尺寸，提高效率，降低系统总成本。

　　SPIFI外设是恩智浦LPC1800系列ARM Cortex-M3微控制器*采用的一种技术。此外，即将面市的新产品还包括低成本Cortex-M0系列和Cortex M4数字符串行控制器(DSC)。

　　SPIFI支持目前市场上大部分串行闪存器件(含四通道读/写产品)，配置编程非常简便，采用4/6引脚设计(取决于串行闪存类型)，支持小型寄存器组，优化内存事务，其软件指令可降低CPU开销，提高内存数据交换效率。

　　SPIFI工作原理

　　图2给出了SPIFI外设的功能框图。SPIFI功能块与微控制器应用的高速总线(AHB)矩阵连接，后者主要用于处理器内核和片上内存。SPIFI将外部SPI闪存内容映射到微控制器内存中。当片上ROM启动代码激活SPIFI接口后，外部SPI内存与核心处理单元上的片上内存功能*相似。

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